Tiwei Wei
University of California-Los Angeles, CA·Engineering
Modern computer chips are increasingly built in 3D, with many layers stacked and wired tightly together. This advanced 3D packaging improves performance, but it also traps heat and creates mechanical stress deep inside the stack.
- Fields
Engineering
Materials Science
Physics
- Topics
3D packaging
advanced packaging
semiconductor packaging
- Grants
- 1 known grant, through Aug 2028
What they work on
- Design photonic waveguide layouts, tiny light channels built into a 3D packaging test vehicle, that preserve strong micro-Raman scattering signals without altering the local thermal and mechanical environment.
- Establish a reliable fabrication process for 3D semiconductor packages with integrated photonic waveguides that deliver an optical probe to buried regions.
- Demonstrate in situ, submicron measurement of local temperature rise and thermal-mechanical stress inside operating 3D packages using micro-Raman spectroscopy, to identify hotspots and stress concentrations.
More about the research
Both slow transistors down and make devices fail sooner. The hottest and most stressed spots are buried under layers of components, so it is hard to measure what is happening inside.
Why it matters
Overheating and mechanical stress inside stacked chips reduce transistor performance and speed up device failure. A way to see temperature and stress inside working 3D packages could help chip makers and packaging engineers find weak spots and design more reliable semiconductor devices. It could also give inspection teams a new set of tools.
Known grants
From NIH and NSF research grants. Labs often have other funding we can't see.
Closest labs
David Cahill
University of Illinois Urbana-Champaign, IL·Materials Science
Develop lock-in infrared thermography, which tracks rhythmic temperature changes with an infrared camera, to measure thermal resistance in three-dimensional integrated circuit die stacks.
Yuping Zeng
University of Delaware, DE·Engineering·Early-career
Find the material, surface and interface causes that make GaN-on-Si high electron mobility transistors perform worse than GaN-on-SiC devices, by linking fabrication process steps to measured device performance.
Amir Safavi-Naeini
Stanford University, CA·Engineering
Design and fabricate multilayer oxide-clad thin-film lithium niobate waveguides and resonators with low loss, high nonlinearity and low sensitivity to fabrication imperfections.
The school
University of California-Los Angeles: 84 labs on PI Pages, $1.9B a year on research, 803 research doctorates a year.
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