David Cahill
University of Illinois Urbana-Champaign, IL·Materials Science
Modern chips are getting taller. High-performance microelectronics now stack silicon dies, the individual chip pieces, into three-dimensional assemblies so that logic and memory can exchange data quickly.
- Fields
Materials Science
Engineering
Physics
- Topics
lock-in thermography
infrared thermography
thermal resistance
- Grants
- 1 known grant, last ended Oct 2026
What they work on
- Develop lock-in infrared thermography, which tracks rhythmic temperature changes with an infrared camera, to measure thermal resistance in three-dimensional integrated circuit die stacks.
- Build and validate an analytical model of heat conduction through multilayer die stacks to interpret thermography measurements.
- Refine a fast measurement approach that extracts the thermal resistance of individual interconnect layers, aiming for a metrology tool usable in industry.
More about the research
But each interface between dies resists the flow of heat. A stack can need to shed up to a kilowatt of heat into its heat exchanger, and poor heat transfer limits device performance across the industry. Engineers need measurement tools that work in an industrial setting to design cooling, monitor assembly and analyze failures.
Why it matters
Overheating limits how fast stacked 3D chips can run. A practical tool for measuring heat flow through each layer could help chip makers and packaging engineers design better cooling. It could also help them monitor assembly quality and diagnose failures, speeding the development of high-performance microelectronics.
Known grants
From NIH and NSF research grants. Labs often have other funding we can't see.
Closest labs
Yan Wang
University of Nevada-Reno, NV·Engineering·Early-career
Determine how wave-like phonons, atomic vibrations that carry heat, travel, scatter and become trapped in periodic, quasi-periodic and aperiodic structures, combining spectral phonon analysis with phonon spectroscopy.
Tiwei Wei
University of California-Los Angeles, CA·Engineering
Design photonic waveguide layouts, tiny light channels built into a 3D packaging test vehicle, that preserve strong micro-Raman scattering signals without altering the local thermal and mechanical environment.
Jing Zhang
Rochester Institute of Technology, NY·Engineering
Advance interdisciplinary semiconductor research in four tracks spanning physics and materials science, micro- and nanoelectronics, optoelectronics and photonics, and integrated circuits and packaging, all built on CMOS chip technology.
The school
University of Illinois Urbana-Champaign: 41 labs on PI Pages, $907M a year on research, 870 research doctorates a year.
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