Abhijit Chatterjee
Georgia Institute of Technology, GA·Engineering
Computer chips now hold billions of transistors and are pushed to low voltages and tiny sizes, which makes them more likely to have hidden manufacturing flaws or to suffer random errors while running. A faulty chip that slips through testing can fail in the field, and for artificial intelligence (AI) systems in cars or robots, such failures can be dangerous.
- Fields
Engineering
Computer Science
- Topics
integrated circuit testing
VLSI test
cell aware test
- Grants
- 2 known grants, through Sep 2027
What they work on
- Develop post-manufacture test and tuning algorithms for deep neural networks running on analog crossbar arrays, recovering accuracy lost to manufacturing variation in seconds rather than hours and detecting shorts and opens.
- Build on-line methods that detect, diagnose and correct radiation- and noise-induced soft errors in digital and analog AI accelerators with near-zero latency and no retraining, across transformers, recurrent and spiking networks.
- Replace exhaustive circuit simulation in cell aware test with analytical reasoning to generate compact tests for defects inside standard cells across wide ranges of defect resistance.
- Capture how a single defect's timing delay spreads across interconnected cells, so that generated tests reduce escapes of timing faults in deeply scaled integrated circuits.
More about the research
The projects develop algorithms that find defective chips more cheaply after manufacture and keep AI hardware working correctly despite flaws and noise.
Why it matters
Cheaper, more complete chip tests could reduce the number of faulty integrated circuits reaching computers, vehicles and defense systems, and lower manufacturing and test costs for chip makers. Fast tuning and real-time error correction for AI accelerators could make AI hardware dependable enough for safety-critical uses such as transportation and robotics, while supporting energy-efficient analog designs.
Known grants
From NIH and NSF research grants. Labs often have other funding we can't see.
Closest labs
Sumit Jha
University of Florida, FL·Computer Science
Develop formal verification methods that prove neural networks run correctly when accelerated on analog in-memory computing hardware, which can be more error-prone than standard CMOS chips.
Deliang Fan
Arizona State University Campus Immersion, AZ·Engineering·Early-career
Design, fabricate and validate a hybrid in-memory computing chip that combines RRAM, a non-volatile resistive memory, with SRAM to run deep neural networks with high energy efficiency.
Qian Yu
University of California-Santa Barbara, CA·Engineering
Develop a highly compressed training method for physics-informed neural networks (PINNs) that uses only forward passes and no backpropagation, so it can run on photonic chips without photonic memory.
The school
Georgia Institute of Technology: 50 labs on PI Pages, $1.5B a year on research, 572 research doctorates a year.
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